1. Field of the Invention
The present invention relates to a static random access memory cell, and more particularly, to a disturb-free static random access memory cell operable under a wide range of supply voltages, and having a high density and high data accessing speed.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a conventional static random access memory. The static random access memory comprises a static random access memory cell 10 and a sense amplifier (not shown). The conventional static random access memory cell 10 comprises six field effect transistors, i.e., a so-called 6-T static random access memory cell. Me and Mf are the access transistor (also called pass-transistor). The latch circuit 11 comprises two inverters 11a and 11b, and each inverter comprises an N-type Field Effect Transistor (NFET) and a P-type Field Effect Transistor (PFET). When a logic value (i.e., the bit value stored) in the static random access memory cell 10 is read, the voltage level of the first bit line 12 and the second bit line 16 are charged to a high voltage level. Then, the voltage level of the word line 14 is raised to a high voltage level to turn on the field effect transistors Me and Mf. Depending on the data stored in the static random access memory cell, one of the storage node (either Na or Nb) will be at logic “Low” voltage level, and the corresponding bit line (either the first bit line 12, or the second bit line 16) will be pulled down. The sense amplifier of the static random access memory then determines the logic value stored in the latch circuit 11 according to the voltage levels of the first bit line 12 and the second bit line 16.
In addition, when a logic value (i.e., the bit value being written) is written to the static random access memory cell 10, the voltage level of the word line 14 is charged to a high voltage level to turn on the field effect transistors Me and Mf. Then, if the bit value being written is logic 1, the voltage level of the first bit line 12 is charged to the high voltage level and the voltage level of the second bit line 16 is discharged to the low voltage level; or if the bit value being written is logic 0, the voltage level of the first bit line 12 is discharged to the low voltage level and the voltage level of the second bit line 16 is charged to the high voltage level. Accordingly, the logic value (i.e., the bit value being written) is written into the latch circuit 11 by complementing the voltage levels of the first bit line 12 and the second bit line 16.
When the bit value of logic 0 is read from the latch circuit 11, the logic 0 stored in the latch circuit 11 discharges the voltage level of the bit line coupled to the latch circuit 11 to the low voltage level. However, the electric charge on the bit line is also poured to the cell storage node (Na or Nb) of the latch circuit 11 coupled to the bit line when the bit value of logic 0 is read from the latch circuit 11. Furthermore, since the access (pass) transistor (Me or Mf) forms a voltage divider with the pull-down N-type field effect transistor of the inverter in the latch circuit 11, the cell storage node (Na or Nb) of the latch circuit 11 may suffer from a disturb voltage, which is called the read-select-disturb phenomenon. If the disturb voltage level is large enough to flip the opposite side inverter of the latch circuit 11, the logic value stored in the latch circuit 11 could be changed. Accordingly, the sense amplifier may read a wrong value from the latch circuit 11.
Furthermore, in the process of reading or writing the bit value into the latch circuit 11, when the voltage level of the word line 14 is charged to the high voltage level, all of the access (pass) transistors in the static random access memory cells coupled to the word line 14 are turned on, then the static random access memories that are coupled to the word line 14 but not coupled to the bit line 12 and 16 may also suffer from a disturb phenomenon similar to the read-select-disturb phenomenon. Therefore, the logics values stored in the aforementioned static random access memory cells could be changed, which is called the half-select-disturb phenomenon. When the half-select-disturb phenomenon occurs in the process of reading, the half-select-disturb phenomenon is also called read half-select-disturb; and when the half-select-disturb phenomenon occurs in the process of writing, the half-select-disturb phenomenon is also called write half-select-disturb.
Since the access (pass) transistors (e.g., the transistors Me and Mf in FIG. 1) have both the role of passing the write-in data into the latch circuit 11 and passing the read-out data to the bit lines, the stability of the data stored in the latch circuit 11 and the data write-in speed of the static random access memory is a trade-off. To reduce read-select-disturb and half-select-disturb, the access (pass) transistors need to be sized down. On the other hand, to improve write margin and write-in speed, the access (pass) transistors need to be sized up. In addition, the supply voltage level of the static random access memory is getting lower in advanced manufacturing processes, and therefore the threshold voltage (VT) of the field effect transistor in the static random access memory is lower also, while the spread of VT (called VT scatter) becomes larger. Accordingly, the stability of the data stored in the latch circuit 11 is more easily affected by the spread (variation) of the threshold voltage (VT) of the field effect transistor in the static random access memory. Therefore, providing a stable and high speed static random access memory cell is a significant concern in this field.